Many electronic and computer-related products (i.e., semiconductors, computer hard disks, etc.) require highly polished surfaces in order to achieve optimum operational characteristics. Recent growth in the implementation of integrated circuit devices has generally resulted in a corresponding increase in demand for semiconductor wafers from which integrated circuit chips (“IC's”) are made. The need for higher density IC's, as well as the need for higher production throughput of IC's on a per-wafer basis, has resulted in a need for increasing the planarity of semiconductor wafer surfaces both during initial production of semiconductor wafers as well as during the actual fabrication of an IC on the wafer surface. This need for increased planarity of semiconductor wafer surfaces presents unresolved challenges in the Chemical Mechanical Planarization (“CMP”) art (i.e., Cost-of-Ownership considerations), such as, for example, decreasing the slurry consumption.
The production of IC's generally begins with the creation of high-quality semiconductor wafers. During the IC fabrication process, the wafers typically undergo multiple masking, etching, and deposition process steps. After each deposition, the layer is etched to create circuit component features. Because of the high precision required in the manufacturing of IC's, an extremely planar surface is generally needed on at least one side of the semiconductor wafer to ensure proper accuracy and performance of the microelectronic structures created at the wafer surface.
As multiple circuit layers are iteratively exposed and developed, the outermost surface of the substrate becomes increasingly non-planar. This occurs because the distance between the outer surface and the underlying substrate is greatest in regions of the wafer substrate where the least lithographic etching has occurred, and least in regions where the greatest etching has occurred. With a single circuit-pattern layer, these surface variations comprise a series of peaks and valleys where the vertical differential between the highest peak and lowest valley may be on the order of several thousand Angstroms. With the construction of multiple circuit layers, this vertical differential accumulates and becomes increasingly divergent—reaching several microns and resulting in the production of defective IC devices.
In general the need for highly planar wafer surfaces becomes increasingly important as the size of the IC's decrease and the number of microstructures per IC increase. In order to manufacture ultra-high density IC's, CMP processes are employed to provide a suitably adapted surface that is both highly planar and uniform across substantially the entire surface of the wafer.
An exemplary wafer substrate for lithographic etching of circuit patterns may be constructed by coating a circular, flat, silicon wafer with a film of metal such as aluminum. A layer of photoresist is then placed over the metal layer. A photolithographic apparatus is then typically employed to expose the photoresist to electromagnetic or particle-beam radiation to produce a patterned photoresist layer. Exposed portions of the metal layer are then chemically etched leaving behind circuit component features. The remaining photoresist is then removed to permit further processing.
A second layer of circuit componentry may then be created, for example, by depositing an insulative layer (i.e., silicon dioxide) over the previously developed circuit features. The outer surface of the second insulative layer topologically conforms to the variations created by the etching of the underlying circuit pattern. This creates a series of peaks and valleys on the outermost surface of the second (e.g., dielectric) layer. The resulting complexity and variation of topological features tends to increase with the exposure and etching of multiple component layers.
Photolithographic techniques used to pattern the photoresist typically have a depth of focus of about 0.2 to 0.4 microns for sub-half-micron features. If the photoresist layer is sufficiently non-planar (i.e., if the maximum vertical differential of any peak and any valley on the outer surface is greater than the depth of focus of the imaging device), then it will generally not be possible to properly focus the image onto the wafer to create the pattern for the next layer of componentry. Even where the imaging apparatus may be adapted to accommodate the non-planarity created by any single patterned layer within the range of the device's depth of focus, after the deposition of a sufficient number of circuit layers, the maximum vertical differential will eventually exceed the imaging apparatus' depth of focus and, therefore, compromise its ability to accommodate the non-planarity.
CMP machines have been developed to polish or planarize silicon wafer surfaces to the flat condition desired for manufacture of IC components, and the like. For a general discussion of conventional CMP processes and devices, see U.S. Pat. No. 4,805,348, issued in February 1989 to Arai et al.; U.S. Pat. No. 4,811,522, issued in March 1989 to Gill; U.S. Pat. No. 5,099,614, issued in March 1992 to Arai et al.; U.S. Pat. No. 5,329,732, issued in July 1994 to Karlsrud et al.; U.S. Pat. No. 5,476,890, issued in December 1995 to Masayoshi et al.; U.S. Pat. Nos. 5,498,196 and 5,498,199, both issued in March 1996 to Karlsrud et al.; U.S. Pat. No. 5,558,568, issued in September 1996 to Talieh et al.; and U.S. Pat. No. 5,584,751, issued in December 1996 to Kobayashi et al., all of which are incorporated herein by reference.
Chemical mechanical polishing or planarizing of a surface of an object may be desirable for several reasons. For example, chemical mechanical polishing is often used in the formation of microelectronic devices to provide a substantially smooth, planar surface suitable for subsequent fabrication processes such as photoresist coating and pattern definition. Chemical mechanical polishing may also be used to form microelectronic features. For example, a conductive feature such as a metal line or a conductive plug may be formed on a surface of a wafer by forming trenches and vias on the wafer surface, depositing conductive material over the wafer surface and into the trenches and vias, and removing the conductive material on the surface of the wafer using chemical mechanical polishing, leaving the vias and trenches filled with the conductive material.
A typical chemical mechanical polishing apparatus suitable for planarizing the semiconductor surface generally includes a wafer carrier configured to support, guide, and apply pressure to a wafer during the polishing process; a polishing compound such as a slurry containing abrasive particles and chemicals to assist removal of material from the surface of the wafer; and a polishing surface such as a polishing pad. In addition, the polishing apparatus may include an integrated wafer cleaning system and/or an automated load and unload station to facilitate automatic processing of the wafers.
In an exemplary prior art CMP polishing method, one side of a silicon wafer is attached to a flat surface of a wafer carrier or chuck with the other side of the wafer pressed against a flat polishing pad. In general, the exposed surface of the pad incorporates an abrasive such as, for example, cerium oxide, aluminum oxide, fumed/precipitated silica, or other particulate abrasives, while the underlying support material may be formed of various commercially available compositions such as, for example, a blown polyurethane (i.e., the IC, SUBA IV and GS series of polishing pads available from Rodel Products, Phoenix, Ariz., USA; Cabot Microelectronics, Aurora, Ill., USA; and/or Thomas West, Sunnyvale, Calif., USA) or such other materials that are known in the art.
During the polishing or planarization process, the workpiece (e.g., silicon wafer) is typically pressed against the polishing pad surface while the pad rotates about its principle axis in the presence of a polishing compound. In particular, the wafer is placed in the carrier such that the surface to be polished is placed in contact with the polishing surface and the polishing surface and the wafer are moved relative to each other while slurry is supplied to the polishing surface. Additionally, in order to improve polishing effectiveness, the wafer may also be rotated about its principal axis and oscillated over both the inner and outer radial surfaces of the polishing pad. Moreover, an orbital polisher may be employed to further increase polishing uniformity and effectiveness. The hardness and density of the polishing pad depends on the material that is to be polished and the degree of precision required in the polishing process.
CMP is a fairly complex process that differs substantially from simple wet sanding. In the CMP process, polishing slurry, including an abrasive and at least one chemically reactive agent, is spread on the polishing pad to provide an abrasive chemical solution at the interface between the pad and wafer substrate. The chemically reactive agent in the slurry reacts with the outer surface of the substrate to form reactive sites. The interaction of the polishing pad and abrasive particles with the reactive sites results in polishing of the wafer substrate; that is, Chemical Mechanical Planarization or Polishing occurs when pressure is applied between the polishing pad and the workpiece being polished where the mechanical stresses and the abrasive particles within the slurry create mechanical strain on the chemical bonds on or near the surface being polished, rendering the chemical bonds more susceptible to chemical attack or corrosion (e.g., stress corrosion).
After the mechanical stresses weaken the chemical bonds on the surface of the workpiece, chemical agent(s) in the slurry will attract certain atoms from the workpiece surface, thereby removing part of the surface material (e.g., chemical leaching). Consequently, microscopic regions are selectively removed from the surface being polished, thereby enhancing the planarity of the polished workpiece surface. Very small deviations in the uniformity of the pressure applied to the wafer substrate across the surface of the substrate can result in defects and imperfections in the planarization process. Planarization, however, need only be performed when necessary: (1) to prevent the peak-to-valley differential from exceeding the depth of photolithographic focus; (2) to minimize metal loss (i.e., for Cu and W CMP) in lines and/or vias by avoiding dishing and erosion; or, (3) any time a new layer is deposited over a previously developed circuit layer.
A suitably adapted and effective CMP process may generally be considered as one that provides a high polishing rate which generates a substrate surface that is both finished (e.g., lacks small-scale roughness) and flat (e.g., lacks large-scale topographic differentials). The desired polishing rate, finish and flatness has previously been manipulated, for example, by selection of the pad and slurry combination; the relative speed between the substrate and pad; the force pressing the substrate against the pad; and the method of introducing the slurry to the pad-wafer interface.
An additional consideration in the production of IC's is process/product stability (e.g., quality control). To achieve a high yield (e.g., low defect rate), each developed circuit layer should generally be polished under substantially reproducible conditions so that each IC is substantially indistinguishable from any other IC produced from a different wafer lot. The realization of improved methods for distribution and control of a suitably adapted slurry composition is therefore important.
FIG. 13 shows post-CMP wafer profiles obtained with both a 1501-50 and an SS-12 slurry in a prior art conventional 300 mm CMP process. In comparison to the 1501-based oxide process, lower removal rates and higher non-uniformity were observed with the SS-12-based oxide process. Due to the SS-12 fumed silica particulate abrasive having a larger average cross-sectional diameter, it is generally thought that the SS-12 slurry exhibits this lower removal rate and higher non-uniformity as a result of difficulties experienced by SS-12 particles in populating the area at the pad-wafer interface during a high pressure CMP polish. A prior art conventional polishing pad (FIG. 12), having X-Y grooving patterns with ¼ inch land-space between grooves and slurry delivery channels located at the intersection of the X-Y grooves, was used. A certain amount of the feed slurry spreads out along the X-Y grooves without participating in the polishing process due to an inability of the slurry to penetrate the grooves to populate the land areas. This is especially the case for slurries delivered through distribution holes which are closer to the edge of the polish pad. Accordingly, an anisotropic distribution of slurry in the peripheral region of the wafer edge is observed for both the 1501 and the SS-12 based processes, which results in what is termed a ‘slow band’ region as shown, for example, in FIG. 13 from about 120 mm to 150 mm and −120 mm to −150 mm.
Additionally, for Cu processes, it has been observed that slurries on orbital and rotational CMP platforms may demonstrate different polish characteristics as well. For example, polish rates and selectivities to Cu, Ta and TEOS, using the same slurry, can turn out quite differently on any two platforms. Moreover, passivation issues during clearing and re-polishing may yield different results as well. It should also be here noted that feature-scale planarization studies have shown less over-polish sensitivity on the orbital platform.
Several prior art processes have been devised to optimize CMP polish behavior. For example, selectivities have been previously achieved by varying, for example, slurry flow rate, polish pressure and orbit speed; however, such control is generally limited with the same process variables also being used to optimize, for example, the polish rate, uniformity, and planarity parameters.
With respect to polish performance, abrasive-free slurries have demonstrated significantly less Cu and TEOS loss. It is generally considered that ‘through-the-pad’ delivery of abrasive-free slurries provides for this improved performance; however, even in this case, it would be desirable to have, for example, a substantially independent mechanism for increasing the Cu removal rate.
Presently known polishing techniques are unsatisfactory in several regards. For example, during polishing, the polishing agents may not be deposited evenly over the entire surface of the polishing pad, which can result in dry spots forming on the polishing pad. Consequently, the polishing effect of the pad may rendered non-uniformity across the surface of the workpiece. Additionally, the removal of surface particles from the workpiece tends to significantly alter the chemical composition of the slurry during the polishing cycle. Moreover, the processing of workpieces may require the deposition of multiple polishing agents from multiple sources with each source potentially causing: (1) the polishing agents to distribute differently across the surface of the polishing pad; and (2) unintended cross reaction(s)—further altering the chemical composition of the slurry.
Still another significant consideration with respect to polishing performance is the Cost-of-Ownership. For example, when considering the cost of processing a wafer, consumable costs may be appreciable and often can exceed that of the polishing tool itself. In particular, the cost of polishing slurry may become a matter of some importance. It is therefore desirable to deliver polishing slurry to the polishing surface in as efficient a manner as possible.
In view of the foregoing, there is a need for a method and apparatus which optimizes polishing throughput while providing for improved surface planarity and finish by controlling: (1) the chemistry of the slurry composition at any given time in the polishing cycle; and (2) the distribution of the slurry to the land areas of a polishing pad to permit a higher degree of planarization and uniformity of material removed over substantially the entire surface of a processed workpiece.